1. Field of the Invention
The present invention relates to a semiconductor device having a circuit pattern constituted by a plurality of circuit blocks having the same structure and arranged regularly.
2. Description of the Related Art
A typical dynamic semiconductor memory device has, as a core section, a memory array 10, a row decoder 11 and a column decoder 12, as shown in FIG. 1. The memory array 10 comprises a plurality of dynamic memory cells having the same structure and arranged in rows and columns, a plurality of word lines WL each connected to the memory cells in a corresponding row, and pairs BLP of bit lines BL1 and BL2 each connected to the memory cells in a corresponding column. The row decoder 11 selects word lines WL in accordance with row address signals, to activate the memory cells in the rows connected to the selected word lines WL. The column decoder 12 selects bit line pairs BLP in accordance with column address signals, so as to transfer write data supplied from an external section to the memory cells connected to the selected bit line pair BLP, or readout data read out from the memory cells connected to the selected bit line pair BLP to the external section.
In this type of semiconductor memory device, the word lines WL are formed over an insulated surface of a semiconductor substrate. The bit lines BL (i.e., BL1 and BL2) are formed on an insulating film that covers the word lines WL. In the case where the word lines WL are formed of polysilicon, a plurality of metal wiring lines AL (not shown) are further formed over an insulating film that covers the bit lines BL, thereby reducing the degree of delay of signals transmitted through the word lines WL. The metal wiring lines AL extend along the word lines WL and are connected to the corresponding word lines WL within contact regions CT arranged at regular intervals. In FIG. 1, points P indicate locations of connection between the metal wiring lines AL and the word lines WL. As shown in FIG. 2, the distance between adjacent two bit lines BL, with the contact region CT interposed therebetween, is set to a greater value L2, than a regular value L1 of the distance between the adjacent two bit lines BL with no contact region interposed therebetween.
A process of manufacturing the bit lines BL will now be described.
First, a metal layer (or a polycide layer of polysilicon and refractory metal) is deposited on the insulating layer covering the word lines WL, and the metal layer is patterned to form the bit lines BL. In the patterning step, a resist film is coated on the metal layer, and the resist film is selectively exposed with use of a mask film that defines the bit lines BL. Thus, a resist pattern can be formed. Then, the metal layer is subjected to dry etching, with the resist pattern used as a mask. Those portions of the metal layer, which are caused to remain, serve as the bit lines BL.
The reduction in size of memory cells is very important to increase the degree of integration of a semiconductor memory device. The design rules of a core section are much stricter that those of the other part. Where the regular distance L1 between bit lines BL is designed to have a very small value, the exposure light amount, with which a resist film is exposed, needs to be greater than a normal exposure light amount. Because, in the case where the normal exposure light amount is insufficient, the distance between the bit lines BL results in a narrower than the designed value. The increase of the exposure light amount makes it difficult to obtain the designed value of the width of the outermost bit lines BL in the memory array 10, and the designed value of the widths of (the distance L2) of adjacent two bit lines between which the contact region CT is interposed. In other words, as shown in FIG. 2, portions (indicated by hatching) of bit lines BL, which adjoin a wide space, are undesirably eliminated, and consequently the width of each of these bit lines BL becomes smaller than that of each of the other bit lines BL. This unbalances the wiring capacitances between the paired bit lines BL1 and BL2 within the memory array 10, and causes the potential differences which are set at the bit line pairs BLP in accordance with the read out data, to vary depending on the unbalance in wiring capacitance. As a result, sense margins of sense amplifiers (not shown) for detecting the potential differences are lowered.
In the case where a plurality of wiring lines are superposed over a semiconductor substrate, with insulating layers interposed therebetween, an upper insulating layer tends to have a recessed portion in a region corresponding to a contact hole formed in a lower insulating layer. FIG. 3 shows a wiring line CF (e.g. the metal wiring line AL) formed in the vicinity of the contact hole HL, and FIG. 4 illustrates the step of forming the wiring line CF. The wiring line CF is formed by patterning a metal layer MT shown in FIG. 4. In the patterning step, a resist film RS is formed on the metal layer MT, and the resist film RS is exposed with use of a mask film FL. At this time, light beams are scattered due to unevenness of the resist film RS, the portion of the resist film which must be masked by the mask film FL would be exposed. As a result, if the metal layer MT is etched with use of a resist pattern as a mask, which is obtained after removing the exposed part of the resist film, RS the hatched areas shown in FIG. 3 are unnecessarily removed.